Career

Join LFC: Shaping the Future of India's Semiconductor Dominance

LFC is a fabless semiconductor company headquartered in Bangalore India, specializing in high-performance Timing, Interface, and Power Management Integrated Circuits. We focus on transforming the Automotive, Industrial, and HPC/Data Center markets. Our vision is clear: To be the Future of India’s Fabless Semiconductor Revolution, and we need passionate individuals who believe in India's semiconductor mission of positioning India as a trusted partner in the global semiconductor supply-chain and strive towards achieving this goal.

Why Work at LFC?

Innovation at the Forefront

Work on cutting-edge ICs powering tomorrow's technologies in automotive, industrial, and HPC / data center industries.

Career Growth

Access continuous learning, mentorship, and opportunities for professional development.


Collaborative Culture

Join a team that values diverse perspectives and creative problem-solving.

Impact

Be part of a company driving India’s global leadership in semiconductor innovation.

Who We're Looking For

We are building a team of creative, competent and highly motivated individuals who welcome a challenge and are willing to learn and lead.

Our Promise to You

At LFC, we offer competitive pay and a dynamic work environment that fosters growth. Join us and contribute to India’s leadership in the semiconductor industry.

Explore Our Openings

Take the next step in your career and help shape the future of
semiconductor technology.

Location: Bengaluru, India
Job Type: Full-Time
Experience: 8+ years in Power Management IC Design

As a Senior Analog Mixed-Signal Design Engineer at LFC, you will play a key role in designing advanced Power Management ICs (PMICs) using state-of-the-art semiconductor technologies. You will leverage your expertise in high-voltage BCD (Bipolar-CMOS-DMOS) processes to drive the development of efficient, reliable, and high-performance PMIC solutions for automotive, industrial, and data center applications.

  • Lead the design of analog and mixed-signal circuits for PMICs, including voltage regulators, DC-DC converters, LDOs, and power sequencing circuits.
  • Develop and optimize designs using high-voltage BCD processes, ensuring robust performance in high-power, high-efficiency environments.
  • Work closely with cross-functional teams (layout, verification, test) to ensure smooth execution from design to silicon validation.
  • Provide guidance and mentorship to junior engineers, fostering a culture of excellence and continuous learning.
  • Conduct detailed circuit simulations, performance analysis, and design verification to ensure compliance with specification and industry standards with onus on systematic documentation to ensure performance and traceability
  • Work on the full product lifecycle, from conceptualization through to production, with a focus on reliability and long-term performance.
  • Stay updated with the latest advancements in semiconductor technology and PMIC design methodologies.

  • 8+ years of hands-on experience in analog and mixed-signal design, specifically in the development of Power Management ICs.
  • Strong expertise in high-voltage BCD semiconductor processes (ideally 20V and above) for PMIC design.
  • In-depth knowledge of power management topologies including DC-DC converters, LDOs, PMU, and voltage regulation circuits.
  • Proficiency in analog design tools (e.g., Cadence, Spectre, Maestro etc) and simulation techniques.
  • Solid understanding of device physics, layout considerations, and parasitic effects in high-voltage and high-performance designs.
  • Experience with characterization, debugging, and lab validation of analog/mixed-signal circuits.
  • Excellent problem-solving skills, with the ability to troubleshoot and optimize complex analog circuits.
  • Strong communication skills with the ability to collaborate effectively across teams and mentor junior engineers.

  • Master’s or PhD in Electrical Engineering, VLSI Design
  • Familiarity with automotive, industrial, or data center PMIC applications.
  • Knowledge of system-level design, including thermal and mechanical design considerations for PMICs.
  • Experience with mixed-signal verification tools (e.g., MATLAB, Simulink).

If you're passionate about developing industry-leading semiconductor products designed in India, we encourage you to apply to Info@l5cartronics.com with a short cover letter and your resume.

Location: Bengaluru, India
Job Type: Full-Time
Experience: 8+ years in Phase-Locked Loop (PLL) Design

As a Senior Analog Mixed-Signal Design Engineer at LFC, you will play a key role in the design and development of advanced Phase-Locked Loops (PLLs), particularly fractional- N PLLs, using state-of-the-art CMOS process technologies. Your work will focus on designing high-performance PLLs for a wide range of applications, from communications to high-speed signal processing, and beyond. You will be a key contributor to the development of cutting-edge timing solutions that push the boundaries of frequency generation, synchronization, and stability.

  • Design and optimize fractional-N PLLs, focusing on ultra-low jitter, high-frequency stability, and high-precision phase synchronization using the latest CMOS process technologies.
  • Develop and integrate key PLL subsystems such as voltage-controlled oscillators (VCOs), phase frequency detectors (PFDs), charge pumps, and loop filters for fractional-N PLL architectures.
  • Work with advanced high-speed CMOS process nodes to deliver high-performance, low- power PLL designs suitable for next-gen communication systems, high-speed data transfer, and precision timing applications.
  • Perform comprehensive simulations and performance analysis, including phase noise and jitter optimization, to ensure PLLs meet system-level specifications with onus on systematic documentation to support performance and traceability
  • Provide technical leadership and mentorship to junior engineers, fostering innovation and best practices in PLL design.
  • Collaborate with cross-functional teams to ensure seamless integration and testing of PLL designs into larger system solutions.
  • Oversee the full design lifecycle, from conceptualization through to silicon validation, ensuring high reliability and performance.
  • Stay up-to-date with emerging trends and innovations in PLL design, contributing to LFC’s competitive edge in the semiconductor industry.

  • 8+ years of experience in analog and mixed-signal design, with a focus on PLLs, specifically fractional-N PLLs.
  • Expertise in designing PLLs in cutting-edge CMOS process technologies
  • Deep understanding of PLL architecture, including fractional-N PLLs, VCOs, phase detectors, charge pumps, loop filters, and jitter performance.
  • Proficiency with analog design tools (e.g., Cadence, Spectre, Maestro) and PLL simulation techniques.
  • Strong analytical skills, including phase noise and jitter analysis, performance optimization, and circuit debugging.
  • Experience in the design and validation of PLLs for high-speed, high-frequency applications.
  • Excellent problem-solving abilities and a strong track record of delivering high-performance, reliable PLLs.
  • Effective communication skills with the ability to work collaboratively across multidisciplinary teams.

  • Master’s or PhD in Electrical Engineering, VLSI Design
  • Familiarity with system-level design and integration of PLLs in advanced communication or signal processing systems.
  • Experience with mixed-signal verification tools (e.g., MATLAB, Simulink) and post-silicon validation.
  • Knowledge of other timing and synchronization technologies, including clock distribution and frequency synthesis.
  • Provide technical leadership and mentorship to junior engineers, fostering innovation and best practices in PLL design.
  • Collaborate with cross-functional teams to ensure seamless integration and testing of PLL designs into larger system solutions.
  • Oversee the full design lifecycle, from conceptualization through to silicon validation, ensuring high reliability and performance.
  • Stay up-to-date with emerging trends and innovations in PLL design, contributing to LFC’s competitive edge in the semiconductor industry.

If you're passionate about developing industry-leading semiconductor products designed in India, we encourage you to apply to Info@l5cartronics.com with a short cover letter and your resume.

Location: Bengaluru, India
Job Type: Full-Time
Experience: 10+ years in Digital Design

As a Senior Digital Design Technical Lead at LFC, you will focus on designing and implementing complex digital systems for fractional-N PLLs, including algorithm development for signal processing, I2C communication, and advanced digital modulation techniques like sigma-delta and pseudo-random sequence generation. You will leverage your experience in digital design and algorithm implementation to create high- performance, low-power solutions for a range of applications, from communication systems to high-speed data processing.

  • Design and implement complex digital systems for fractional-N PLLs, including algorithm development and optimization for frequency synthesis and phase synchronization.
  • Develop and integrate I2C communication protocols, ensuring efficient data transfer and control for PLLs and other digital components.
  • Lead the design and implementation of sigma-delta modulators for fractional-N PLLs, focusing on low noise, high accuracy, and stability in high-speed applications.
  • Implement pseudo-random sequence generators and other advanced digital techniques for system performance optimization and testing.
  • Work with advanced digital design tools (e.g., Verilog, VHDL, SystemVerilog) to develop and simulate high-performance digital circuits.
  • Collaborate with analog design engineers to ensure seamless integration of digital components with analog circuitry, especially in PLL designs.
  • Perform detailed simulation and verification of digital designs, ensuring compliance with system-level specifications, timing, and performance requirements.
  • Mentor and provide technical guidance to junior engineers, promoting best practices in digital design, algorithm implementation, and system-level integration.
  • Stay updated on emerging trends and advancements in digital design, PLL technologies, and signal processing algorithms.

  • 10+ years of experience in digital design, with a strong focus on I2C protocol, fractional-N PLL designs, sigma-delta modulation, and pseudo-random sequence generation.
  • Expertise in algorithm development for digital systems, particularly in the context of PLLs, signal processing, and modulation techniques.
  • In-depth knowledge of fractional-N PLL architectures and sigma-delta modulation techniques for frequency synthesis and jitter minimization.
  • Experience with the design and implementation of I2C communication protocols for high- performance systems.
  • Strong skills in simulation, verification, and timing analysis for digital circuits, using tools like ModelSim, Cadence, or similar.
  • Experience with characterization, debugging, and lab validation of analog/mixed-signal circuits.
  • Strong problem-solving and debugging skills, with the ability to optimize and troubleshoot complex digital systems.
  • Excellent teamwork and communication skills, with the ability to collaborate effectively across multidisciplinary teams.
  • Full chip integration with a digital on top approach and proven track record of technical leadership with multiple tape-outs

  • Master’s or PhD in Electrical Engineering, Digital Design
  • Experience in high-speed digital designs for communication systems, data transfer, or high-performance computing (HPC) applications.
  • Knowledge of mixed-signal verification techniques and tools (e.g., MATLAB, Simulink).
  • Experience in low-power design techniques and high-frequency digital circuit optimization.

If you're passionate about developing industry-leading semiconductor products designed in India, we encourage you to apply to Info@l5cartronics.com with a short cover letter and your resume.

Location: Bengaluru, India
Job Type: Full-Time
Experience: 10+ years in Layout Design, with a focus on PLLs and PMICs in BCD Technologies

As a Senior Layout Design Technical Lead, you will be responsible for driving the physical layout design of high-speed PLLs and PMICs, ensuring that designs meet performance, power, area, and reliability requirements. You will utilize your expertise in BCD process technologies to lead the layout design for complex circuits, providing technical leadership to a team of engineers. Your proven track record in successfully taping out full-chip designs will be essential to the success of this role.

  • Lead the layout design of high-speed PLLs and PMICs, ensuring optimal layout performance, power efficiency, and minimal signal integrity issues.
  • Work with circuit design teams to ensure the successful implementation of high- performance analog, digital, and mixed-signal circuits in the layout.
  • Leverage your expertise in BCD process technologies to manage complex design requirements for high-voltage (HV) and low-voltage (LV) devices, ensuring proper isolation, well-tapping, and design rule compliance.
  • Mentor and guide junior and mid-level layout designers, fostering a collaborative and results-oriented team environment.
  • Perform layout optimization, including power grid design, clock tree synthesis, and signal integrity analysis to meet high-speed PLL and PMIC performance targets.
  • Ensure full-chip integration and validation, working closely with verification teams to conduct sign-off, DRC, LVS, and ERC checks.
  • Take ownership of the taping out process, coordinating with cross-functional teams to ensure successful and timely tapeouts.
  • Drive the adoption of best practices and design methodologies to improve efficiency and quality of the layout design process.
  • Stay up to date with advancements in layout tools, techniques, and BCD process technologies to continuously improve the layout design flow and capabilities.

  • 10+ years of experience in physical layout design with a focus on high-speed PLLs and PMICs, particularly in BCD process technologies.
  • Proven track record of successful full-chip tapeouts, including experience with complex analog, mixed-signal, and power management IC designs.
  • Strong expertise in BCD process technologies, including design for high-voltage (HV) and low-voltage (LV) components.
  • Proficiency in layout design tools such as Cadence Virtuoso, Synopsys IC Compiler, or similar tools.
  • Deep understanding of layout design techniques to optimize performance, area, power, and signal integrity for high-speed PLL and PMIC designs.
  • Extensive experience with layout verification tools (e.g., DRC, LVS, ERC, and parasitic extraction) and ensuring compliance with process design rules.
  • Ability to work closely with cross-functional teams, including circuit designers, verification engineers, and project managers, to deliver high-quality designs on time.
  • Strong problem-solving skills and the ability to troubleshoot complex layout issues efficiently.
  • Excellent communication skills and the ability to provide technical leadership and mentorship to other team members.

  • Master’s or PhD in Electrical Engineering, VLSI Design, or a related field.
  • Experience with advanced process nodes and complex analog/mixed-signal design.
  • Familiarity with power grid design, clock tree synthesis, and layout for low-noise/high- performance designs.
  • Experience in full-chip integration, floor-planning, and multi-chip module design.
  • Knowledge of automated layout optimization techniques and advanced physical design flows.

If you're passionate about developing industry-leading semiconductor products designed in India, we encourage you to apply to Info@l5cartronics.com with a short cover letter and your resume.